MDLL & Slave Delay Line performance analysis using novel delay modeling

In this paper, we present a novel approach to comprehensively verify timing sensitive blocks, specifically Delay Lines and Delay Locked Loops by modelling transient behavior into the RTL. This paper focuses on reduction of simulation time and increase in design turnaround time. Information gathered from a small set of spice simulations is modelled into a Verilog based environment, which gives significant flexibility in terms of test cases, data collection and analysis. Keywords—Delay line; DLL; RTL modelling; DLL verification; Noise and jitter analysis